Technical Deep Dive
Gemmini's architecture is built around a systolic array—a grid of processing elements (PEs) that perform multiply-accumulate (MAC) operations in a pipelined, data-flow fashion. This design is ideal for matrix multiplication and convolution because it maximizes data reuse and minimizes memory bandwidth requirements. The generator allows users to specify the array dimensions (e.g., 16x16, 32x32, 64x64), the data type for each PE (INT8, FP16, FP32), and the depth of local scratchpads and global buffers.
Memory Hierarchy: Gemmini employs a multi-level memory system: a global DRAM interface, a shared scratchpad (typically SRAM), and local PE registers. The scratchpad is partitioned into banks to enable parallel access. The generator also supports tiling—breaking large matrices into blocks that fit in the scratchpad—which is critical for real-world performance.
Chisel and the RTL Generation: Gemmini is written in Chisel, which compiles to Verilog. This allows designers to parametrize the accelerator at a high level (e.g., `val gemmini = GemminiConfig(rows=32, cols=32, dataType=INT8)`) and generate optimized RTL. The repository includes a full test suite, a cycle-accurate simulator, and integration scripts for the Rocket Chip SoC generator.
Performance Benchmarks: The following table compares Gemmini's performance against other open-source accelerators on common edge inference tasks (data from published papers and GitHub documentation):
| Accelerator | Array Size | Data Type | Throughput (GOPS) @ 1GHz | Power (mW) | Area (mm² @ 28nm) |
|---|---|---|---|---|---|
| Gemmini (default) | 16x16 | INT8 | 512 | 250 | 1.2 |
| Gemmini (large) | 64x64 | INT8 | 8192 | 1800 | 8.5 |
| NVIDIA NVDLA (small) | — | INT8 | 1024 | 500 | 2.5 |
| Google Edge TPU (simulated) | 64x64 | INT8 | 4096 | 2000 | 12.0 |
Data Takeaway: Gemmini's small configuration achieves competitive throughput per area and power, but the large configuration scales linearly—a key advantage of the systolic array design. However, NVDLA's dedicated hardware for convolutions can outperform Gemmini on certain layer types (e.g., depthwise convolutions) due to specialized dataflows.
Key Open-Source Repositories:
- ucb-bar/gemmini (⭐1,384): The main repository, including Chisel source, testbenches, and integration with Rocket Chip.
- ucb-bar/chisel3 (⭐3,800+): The hardware construction language used to build Gemmini.
- ucb-bar/rocket-chip (⭐3,200+): The RISC-V SoC generator that Gemmini is designed to plug into.
Key Players & Case Studies
UC Berkeley ASPIRE Lab: Led by Professor Krste Asanović (also a RISC-V co-founder), the lab has a long track record of open-source hardware projects. Gemmini is the latest in a lineage that includes the Rocket Chip generator and the BOOM out-of-order core. The lab's strategy is to provide a complete, open-source AI accelerator that can be used for both research and commercial prototyping.
SiFive and Esperanto Technologies: These RISC-V chip startups have publicly referenced Gemmini as a reference design for their AI accelerators. SiFive's Intelligence series of processors includes optional AI acceleration blocks that share architectural concepts with Gemmini. Esperanto's ET-SoC-1, a 1,000-core RISC-V chip for AI inference, uses a similar systolic array approach, though their implementation is proprietary.
Comparison with Proprietary Accelerators:
| Feature | Gemmini | NVIDIA NVDLA | Google TPUv4i |
|---|---|---|---|
| License | Open-source (BSD) | Open-source (NVIDIA) | Proprietary |
| Programmability | Custom software stack (C++/Python) | NVIDIA's compiler toolchain | TensorFlow/PyTorch via XLA |
| Flexibility | Parametric (size, data type, memory) | Fixed dataflow (convolution-optimized) | Fixed systolic array |
| Ecosystem | RISC-V + Chisel | ARM/x86 + Verilog | Google Cloud |
| Maturity | Academic (pre-silicon) | Production (used in Xavier, Orin) | Production (cloud) |
Data Takeaway: While NVDLA and TPU offer production-ready performance and software ecosystems, Gemmini's open-source nature and parametric flexibility make it the go-to choice for researchers and startups that need to customize the accelerator for novel architectures (e.g., sparsity, mixed-precision, or non-traditional dataflows).
Industry Impact & Market Dynamics
Gemmini is part of a broader trend toward open-source AI hardware, which is challenging the dominance of proprietary vendors like NVIDIA, Intel, and Google. The global AI accelerator market is projected to grow from $10.2 billion in 2023 to $71.3 billion by 2030 (CAGR 32%), according to industry reports. Open-source accelerators like Gemmini are capturing a small but growing share of the edge inference segment, which is expected to reach $15 billion by 2027.
Adoption Drivers:
1. RISC-V Ecosystem Growth: The RISC-V ISA is gaining traction in IoT, automotive, and edge devices. Gemmini provides a natural AI acceleration path for RISC-V SoCs.
2. Startup Cost Reduction: A startup can use Gemmini to generate a custom accelerator without paying millions in licensing fees or hiring a large hardware team.
3. Academic Research: Universities use Gemmini to explore novel architectures (e.g., analog computing, in-memory computing) without building a full chip from scratch.
Market Data Table:
| Year | Open-Source AI Accelerator Market Share (est.) | Gemmini GitHub Stars | Number of RISC-V AI Chip Startups |
|---|---|---|---|
| 2021 | 2% | 450 | 12 |
| 2023 | 5% | 1,100 | 25 |
| 2025 (projected) | 10% | 2,500 | 40 |
Data Takeaway: The correlation between Gemmini's GitHub popularity and the growth of RISC-V AI startups suggests that the open-source accelerator is acting as a catalyst for the ecosystem. However, the 5% market share indicates that proprietary solutions still dominate, especially in high-performance cloud inference.
Risks, Limitations & Open Questions
Chisel Learning Curve: Gemmini's reliance on Chisel is a double-edged sword. While Chisel enables powerful parameterization, it is unfamiliar to most hardware engineers who are trained in Verilog or VHDL. This limits the pool of developers who can contribute or customize Gemmini.
Software Stack Immaturity: Unlike NVIDIA's CUDA or Google's TensorFlow, Gemmini's software stack is rudimentary. It includes a C++ library and a Python wrapper, but lacks a full compiler that can optimize arbitrary neural network graphs. Users must manually tile operations and manage data movement.
Silicon Provenness: Gemmini has been synthesized and tested on FPGAs, but as of mid-2025, no commercial chip has been taped out using Gemmini as the primary accelerator. The risk of bugs or performance bottlenecks in silicon remains.
Scalability to Large Models: Gemmini is designed for edge inference (models up to tens of millions of parameters). For large language models (LLMs) with billions of parameters, the memory hierarchy and bandwidth are insufficient without significant modifications.
Ethical Concerns: Open-source AI accelerators could lower the barrier for malicious actors to build custom hardware for surveillance or autonomous weapons. However, this is a general concern for all open-source hardware, not specific to Gemmini.
AINews Verdict & Predictions
Gemmini is a critical piece of infrastructure for the open-source AI hardware movement, but it is not yet a commercial product. Our editorial judgment is that Gemmini will follow a trajectory similar to Linux in the 1990s: initially dismissed as an academic toy, it will gradually gain adoption in niche markets (edge IoT, automotive, aerospace) where customization and cost are more important than peak performance.
Predictions:
1. By 2027, at least three startups will tape out chips using Gemmini-derived accelerators, targeting applications like smart cameras, drone navigation, and industrial robotics.
2. By 2028, the Gemmini project will merge with the RISC-V Vector Extension (RVV) to provide a unified programming model, reducing the software stack gap.
3. By 2030, open-source AI accelerators (including Gemmini and its derivatives) will capture 15-20% of the edge inference market, driven by the proliferation of RISC-V in IoT devices.
What to Watch: The next major milestone is a successful tape-out of a Gemmini-based chip in a commercial process (e.g., TSMC 28nm or 12nm). If that happens, expect a surge in venture capital interest and a wave of new startups. Until then, Gemmini remains a powerful research tool with immense potential—but it is not yet a threat to NVIDIA's dominance.