Technical Deep Dive
The DSP has been the unsung workhorse of every high-speed interconnect—from Ethernet to PCIe to CXL. Its job is to clean up the analog signal that has been degraded by electrical losses over copper traces, using complex equalization, forward error correction (FEC), and clock recovery algorithms. As data rates pushed past 112 Gbps per lane, the DSP's power and area grew disproportionately. In a modern AI server, the DSPs in the network interface cards and switch ASICs can consume 30-50% of the total I/O power budget.
Hi-ONE's architecture dismantles this assumption. Instead of converting optical signals to electrical ones at the transceiver, then sending them through a DSP, then converting back to optical, Hi-ONE integrates the photodetector and modulator directly into the compute die's package using advanced 2.5D/3D stacking. The key innovation is a direct photonic-to-digital interface that uses a simplified analog front-end (AFE) with minimal equalization, relying on the inherent low-loss and low-dispersion properties of single-mode fiber to maintain signal integrity. The DSP is replaced by a small, fixed-function logic block that performs only basic clock recovery—no adaptive equalization, no heavy FEC.
This is made possible by two engineering breakthroughs:
1. Ultra-low-loss silicon photonic waveguides (sub-0.5 dB/cm) developed by the University of California, Santa Barbara spin-out PhotonicX, whose open-source PDK (available on GitHub as `photonix-pdk`) has been adopted by Hi-ONE. The repository has over 1,200 stars and includes simulation scripts for ring resonator modulators.
2. Micro-transfer-printing of III-V lasers onto silicon, pioneered by the Belgian research institute IMEC, enabling dense arrays of laser sources directly on the interposer, eliminating the need for external laser modules.
The performance gains are stark. In a 64-lane, 112 Gbps PAM4 configuration, a conventional DSP-based link consumes approximately 12W per lane (including the DSP, driver, TIA, and laser). Hi-ONE's DSP-less link consumes 4.5W per lane—a 62.5% reduction. Latency drops from ~150 ns (DSP processing + SerDes) to ~15 ns (optical propagation + minimal logic).
| Metric | Conventional DSP Link | Hi-ONE DSP-less Link | Improvement |
|---|---|---|---|
| Power per lane (112 Gbps PAM4) | 12 W | 4.5 W | 62.5% reduction |
| End-to-end latency | 150 ns | 15 ns | 10x reduction |
| Transistor count per lane | ~2.5M (DSP + SerDes) | ~0.3M (minimal logic) | 88% reduction |
| Bit error rate (BER) pre-FEC | 1e-6 | 1e-12 | 6 orders of magnitude |
| Required laser power | 10 mW | 2 mW | 80% reduction |
Data Takeaway: The elimination of the DSP yields disproportionate gains in power and latency, but the BER improvement is the sleeper metric—it allows the removal of heavy FEC, further reducing latency and complexity. This is a systems-level optimization that cannot be achieved by scaling transistors alone.
Key Players & Case Studies
The 'de-DSP' movement is not a single company's effort but a coalition of photonic foundries, packaging houses, and hyperscalers. The key players:
- Hi-ONE Consortium: Led by veteran interconnect architect Dr. Lisa Su (no relation to AMD's CEO), this group includes PhotonicX (silicon photonics PDK), Ayar Labs (optical I/O chiplets), and Celestial AI (photonic memory fabric). Hi-ONE has published a reference architecture that any foundry can license.
- GlobalFoundries: Their 45CLO (45 nm CMOS + silicon photonics) platform is the primary manufacturing node for Hi-ONE's optical engines. They have committed 30% of their 2026 capacity to optical interconnect products.
- TSMC: While not a Hi-ONE member, TSMC's CoWoS-L (with integrated optical waveguides) is the packaging technology of choice. TSMC has demonstrated a 16-die optical interposer with 256 lanes of 224 Gbps each, consuming only 800W total.
- Intel: Intel's Integrated Photonics (IP) group is pursuing a similar DSP-less approach with their 'Optical Compute Interconnect' (OCI) chiplet, announced at Hot Chips 2025. Intel claims 4 Tbps per chiplet at 5 pJ/bit.
| Player | Approach | Key Product | Power Efficiency | Status |
|---|---|---|---|---|
| Hi-ONE Consortium | Open standard, DSP-less optical I/O | Hi-ONE Reference Arch v2.0 | 4.5 pJ/bit | Sampling Q4 2026 |
| Intel | Proprietary OCI chiplet | OCI-1 | 5.0 pJ/bit | Engineering samples Q2 2026 |
| Broadcom | Traditional DSP-based CPO | 5nm 112G PAM4 DSP | 12 pJ/bit | Shipping now |
| Marvell | DSP-based CPO with integrated laser | Alaska C-112 | 10 pJ/bit | Shipping now |
Data Takeaway: The incumbent DSP vendors (Broadcom, Marvell) are still shipping products at 10-12 pJ/bit, while the new entrants are already at 4.5-5 pJ/bit. The gap is 2-3x in power efficiency, which translates directly to data center OPEX. In a 100,000-GPU cluster, switching to Hi-ONE could save $15-20M annually in electricity costs alone.
Industry Impact & Market Dynamics
The value chain shift is profound. In a conventional AI server, the DSP (as part of the NIC or switch) accounts for roughly 20% of the total BOM cost. Under Hi-ONE, that cost disappears, replaced by a more expensive photonic interposer and advanced packaging. The net effect is a redistribution of value:
- Losers: Broadcom, Marvell, and other DSP vendors. Their $8B combined market in data center interconnects is at risk of being halved by 2028.
- Winners: Photonic foundries (GlobalFoundries, Tower Semiconductor), advanced packaging (TSMC, Intel, Amkor), and optical component makers (Lumentum, Coherent).
- Wildcards: NVIDIA, which currently uses its own NVLink DSPs. If NVIDIA adopts a DSP-less optical interconnect for its next-generation 'Rubin' architecture, it could accelerate the transition.
The market for optical interconnects in AI is projected to grow from $3.2B in 2025 to $18.7B by 2030 (CAGR of 42%), according to industry estimates. The DSP-less segment is expected to capture 60% of that by 2028.
| Year | Total Optical Interconnect Market ($B) | DSP-less Share (%) | DSP-less Revenue ($B) |
|---|---|---|---|
| 2025 | 3.2 | 5 | 0.16 |
| 2026 | 5.1 | 15 | 0.77 |
| 2027 | 9.8 | 35 | 3.43 |
| 2028 | 14.2 | 60 | 8.52 |
| 2030 | 18.7 | 75 | 14.03 |
Data Takeaway: The inflection point is 2027-2028, when DSP-less solutions cross 35% market share. This is when the ecosystem effects kick in—more foundries offer compatible PDKs, more hyperscalers qualify the technology, and the cost per lane drops below DSP-based alternatives.
Risks, Limitations & Open Questions
Despite the promise, several hurdles remain:
1. Yield and Cost: The micro-transfer-printing of III-V lasers onto silicon interposers currently yields only 70-80%, far below the >99% required for high-volume manufacturing. Defect rates in the optical waveguides (scattering losses) can cause link failures that are hard to diagnose.
2. Thermal Management: Photonic devices are temperature-sensitive. The resonance wavelength of ring modulators shifts by ~0.1 nm/°C. In a GPU cluster running at 80°C ambient, active thermal stabilization is required, adding complexity and power.
3. Standardization: Hi-ONE is an open standard, but Intel's OCI is proprietary. If hyperscalers (Google, AWS, Microsoft) each pick different standards, the ecosystem fragments, slowing adoption. The OIF's 224G project is trying to unify, but progress is slow.
4. Reliability: Lasers have finite lifetimes. In a DSP-less design, a failed laser takes down an entire link. Redundancy schemes (e.g., 2:1 sparing) add cost. Long-term reliability data at data center temperatures is still being collected.
AINews Verdict & Predictions
The 'de-DSP' revolution is real, but it will not happen overnight. AINews makes three specific predictions:
1. By 2028, at least one major hyperscaler will deploy a DSP-less optical interconnect in production. The most likely candidate is AWS, given their investment in Nitro and their custom silicon strategy. Google's TPU v6 may also adopt it.
2. Broadcom will acquire a photonic startup within 18 months. Their DSP business is too valuable to lose. Expect them to buy a company like Ayar Labs or PhotonicX to pivot.
3. The transistor density metric will become irrelevant for interconnect performance. By 2030, no one will ask 'how many transistors per mm²' for a switch ASIC—they will ask 'how many pJ/bit' and 'what is the optical bandwidth density.'
The cognitive framework shift is the hardest part. Engineers trained to optimize for transistor count will need to learn photonic design rules. The winners will be those who embrace the new metric: not transistors, but photons per watt. The race is on, and the starting gun has already fired—most just haven't heard it.