Technical Deep Dive
The shift from TOPS-centric design to reliability-centric engineering represents a fundamental architectural rethinking. Traditional automotive chips were either high-performance but non-safety-critical (e.g., infotainment SoCs) or safety-certified but computationally weak (e.g., Infineon TC3xx). The new generation fuses both domains on a single die or package, but this creates a thermal and electrical nightmare: a 200 TOPS AI accelerator can dissipate 50-80W, while a safety MCU must operate below 2W to avoid thermal runaway in a sealed ECU.
Chiplet Architecture as the Enabler
Chiplet technology—pioneered by AMD in the server space—has been adapted for automotive by Chinese firms. Horizon Robotics' Journey 6 series, for example, uses a multi-die design where a 7nm AI compute die (with BPU neural engine) is co-packaged with a 28nm safety microcontroller die via a silicon interposer. This allows the AI die to be fabricated on advanced nodes for density, while the safety die uses mature, radiation-hardened processes. The interposer provides high-bandwidth, low-latency connectivity (UCIe standard) without the cost of monolithic integration.
Key technical challenges addressed:
- Thermal management: The AI die and safety die have different thermal profiles. Chiplet allows independent cooling zones and thermal interface materials.
- Mixed-signal isolation: High-frequency AI switching can inject noise into safety-critical analog circuits. Chiplet enables physical separation and dedicated power domains.
- Redundancy and lockstep: Safety MCUs in Chiplet designs can implement dual-core lockstep (DCLS) with 100% hardware redundancy, while the AI die remains single-threaded for performance.
Memory Bandwidth and Dataflow Efficiency
World models and end-to-end autonomous driving require massive data throughput. Traditional von Neumann architectures bottleneck at memory access. Chinese chip makers are adopting near-memory computing and processing-in-memory (PIM) techniques. Black Sesame Technologies' Huashan series integrates HBM2e memory directly on the interposer, achieving 1.2 TB/s bandwidth—enough to stream 16 camera feeds at 30fps without off-chip DRAM access. This is critical for latency-sensitive functions like emergency braking, where every millisecond of memory latency could mean a collision.
Relevant open-source GitHub repositories:
- Horizon Robotics' OpenExplorer (10k+ stars): A full-stack AI development platform for Journey chips, including model quantization, compiler, and runtime. Recently added support for transformer-based world models.
- SemiDrive's SafetyOS (2.5k stars): An open-source RTOS with ISO 26262 ASIL-D certification artifacts, designed for their E3 series MCUs. Includes lockstep scheduler and memory protection unit (MPU) drivers.
- Nexchip's Chiplet Design Kit (1.8k stars): A set of open-source scripts and PDK files for designing UCIe-based interposers, enabling smaller companies to experiment with Chiplet integration.
Benchmark Data: The Real Performance Metrics
| Metric | Traditional Monolithic SoC | Chiplet-based (Horizon J6) | Chiplet-based (Black Sesame Huashan) |
|---|---|---|---|
| Peak TOPS (INT8) | 128 | 256 | 384 |
| Sustained TOPS (30 min, 85°C) | 72 (56% drop) | 210 (82% retention) | 310 (81% retention) |
| ASIL-D Safety Island | None (external MCU) | Integrated DCLS Cortex-R52 | Integrated DCLS Cortex-R52 |
| Memory Bandwidth (GB/s) | 68 (LPDDR4) | 512 (HBM2e) | 1,200 (HBM2e) |
| Power Efficiency (TOPS/W) | 2.1 | 4.8 | 5.2 |
| Time to Safety Certification | 18 months (external) | 6 months (pre-certified) | 8 months (pre-certified) |
Data Takeaway: Chiplet designs not only sustain higher performance under thermal stress (82% vs 56% retention), but also dramatically reduce safety certification timelines by integrating pre-certified safety islands. The power efficiency advantage (2.3x-2.5x) is critical for electric vehicles where every watt impacts range.
Key Players & Case Studies
Horizon Robotics
Horizon has pivoted from its early focus on pure AI compute to a platform approach. Their Journey 6 chip, sampling since Q4 2024, is already adopted by BYD, Geely, and NIO for L2+ to L3 systems. The company's strategy is vertical integration: they offer not just the chip, but a complete toolchain including a custom compiler (HBDK), a simulation environment (Horizon Sim), and a safety middleware stack certified to ASIL-D. This reduces automakers' integration risk—a key selling point when a single software bug could trigger a recall.
Black Sesame Technologies
Black Sesame's Huashan series targets the high end with 384 TOPS and a unique dataflow architecture that eliminates the need for a separate GPU. Their NPU is designed specifically for transformer-based models (e.g., BEVFormer, UniAD), which are becoming standard in end-to-end autonomous driving. They have secured design wins with SAIC and XPeng, and are developing a next-generation chip using TSMC N5 process with integrated HBM4.
SemiDrive
SemiDrive takes a different approach: they focus on the safety MCU side, offering the E3 series with up to 6 Cortex-R52 cores in lockstep, achieving ASIL-D with 99% diagnostic coverage. Their chips are used in brake-by-wire and steer-by-wire systems from Bosch and ZF. SemiDrive recently announced a partnership with Horizon to create a reference design combining E3 MCUs with Journey AI accelerators via a Chiplet interposer.
Nexchip
Nexchip is a foundry-play: they offer a Chiplet integration service for automotive clients, using their own 28nm and 12nm processes. They have developed a proprietary UCIe-compatible interposer that supports up to 8 chiplets with total bandwidth of 2 TB/s. Their key innovation is a thermal-aware floorplanning algorithm that automatically places hot AI dies near the package edge and cool safety dies near the center, reducing hotspot temperatures by 15°C.
| Company | Key Product | TOPS | Safety Level | Adoption |
|---|---|---|---|---|
| Horizon Robotics | Journey 6 | 256 | ASIL-D (integrated) | BYD, Geely, NIO |
| Black Sesame Tech | Huashan | 384 | ASIL-D (integrated) | SAIC, XPeng |
| SemiDrive | E3 MCU | 0.5 (MCU) | ASIL-D (native) | Bosch, ZF |
| Nexchip | Chiplet Foundry | N/A | N/A | Multiple OEMs |
Data Takeaway: The market is bifurcating: Horizon and Black Sesame compete on AI performance with integrated safety, while SemiDrive owns the pure safety MCU niche. Nexchip's foundry model enables smaller players to enter without massive R&D investment.
Industry Impact & Market Dynamics
The transition to reliability-centric chips is reshaping the entire automotive supply chain. Automakers are no longer selecting chips based solely on datasheet TOPS; they are demanding silicon-proven safety evidence and long-term supply guarantees. This favors companies with deep process expertise and automotive-grade qualification experience.
Market Size and Growth
| Segment | 2024 Revenue (USD) | 2028 Projected Revenue | CAGR |
|---|---|---|---|
| Automotive AI SoCs | $2.1B | $8.5B | 32% |
| Safety MCUs | $1.8B | $3.2B | 12% |
| Chiplet Interposers | $0.3B | $2.1B | 48% |
| Full-stack Tools | $0.5B | $1.8B | 29% |
Data Takeaway: Chiplet interposers are the fastest-growing segment (48% CAGR), reflecting the industry's rapid adoption of heterogeneous integration. Full-stack tools are also growing strongly, as automakers seek to reduce integration complexity.
Business Model Evolution
Chinese chip companies are moving from a transactional chip-selling model to a subscription-based platform model. Horizon, for example, charges a per-vehicle royalty (estimated $50-100 per car) that includes the chip, compiler updates, and access to their simulation cloud. This aligns incentives: Horizon profits when the automaker sells more cars, and the automaker gets continuous software improvements without upfront NRE costs.
Risks, Limitations & Open Questions
Despite the progress, several critical challenges remain:
1. Thermal cycling reliability: Chiplet packages introduce multiple solder joints and underfill interfaces that can fail under repeated thermal cycling (-40°C to 125°C). Current reliability data from Chinese suppliers shows a 2-3x higher failure rate compared to monolithic packages after 1000 cycles. This must improve to meet automotive 15-year lifespan requirements.
2. Security vulnerabilities: The heterogeneous integration creates new attack surfaces. An attacker could potentially inject faults through the interposer's power delivery network, affecting both AI and safety dies. No Chinese chip maker has yet published a comprehensive security threat model for their Chiplet designs.
3. Software ecosystem fragmentation: While full-stack tools reduce integration time, they also lock automakers into a single vendor's ecosystem. This creates a risk of vendor lock-in, especially if the chip maker goes bankrupt or changes direction. The industry needs standardized APIs (e.g., ROS 2 for automotive) to ensure portability.
4. World model inference latency: Even with HBM2e bandwidth, running a 7B-parameter world model at 30Hz inference requires 210 GB/s of memory bandwidth just for model weights, leaving little room for sensor data. Current chips may hit a bandwidth wall within 2-3 years as models scale.
AINews Verdict & Predictions
Verdict: The Chinese automotive chip industry has made a smart, necessary pivot from vanity metrics to engineering fundamentals. The Chiplet-based approach is not just a cost-saving measure—it is the only viable path to simultaneously achieve high AI performance and ASIL-D safety certification without resorting to expensive monolithic designs on bleeding-edge nodes.
Predictions:
1. By 2026, at least three Chinese automakers will announce L3-capable vehicles using domestic Chiplet-based chips. BYD and NIO are the most likely candidates, given their existing partnerships with Horizon.
2. The TOPS metric will become irrelevant for automotive chips within 18 months. Instead, a new composite metric—'Reliable TOPS' (R-TOPS)—will emerge, factoring in sustained performance under thermal stress, safety coverage, and memory bandwidth. Horizon and Black Sesame are already positioning to lead this new benchmark.
3. Chiplet foundry services (like Nexchip) will become the dominant business model for second-tier chip makers. This mirrors the fabless revolution of the 1990s, but applied to packaging. Expect a wave of startups offering specialized chiplets (e.g., radar processing, lidar point cloud) that can be integrated into standard interposers.
4. The biggest winner will not be a chip company, but a toolchain company. The company that provides the best compiler, simulator, and safety certification framework will capture the most value, because automakers care more about time-to-market than raw silicon specs. Horizon's OpenExplorer ecosystem is currently best positioned, but SemiDrive's SafetyOS could disrupt if it gains broader adoption.
What to watch next: The upcoming World Model Challenge benchmark, expected in Q3 2025, will be the first standardized test of automotive chips running end-to-end driving models. The results will reveal which architectures truly handle the dataflow demands of next-generation autonomy. AINews will cover this event live.